Amplifying circuit with variable load drivability

ABSTRACT

The present invention relates to an amplifying circuit that can change load drivability responding to load conditions, and reduce power consumption. The amplifying circuit according to the present invention comprises an amplifying means that amplifies input signals a first time to generate a first and a second amplified signals through a first and a second transistors, and further amplifies the first and second amplified signals once again through a third and a fourth transistors, for final outputs; a detecting means for detecting the first and second amplified signals from the amplifying means and generating a first and a second detection signals; and a load drivability control means that is controlled by the first and second detection signals from the detecting means to change load drivability of the amplifying means.

FIELD OF THE INVENTION

The present invention relates to an amplifying circuit, and, moreparticularly, to a 2-stage amplifying circuit that has variable loaddrivability responding to load conditions and smaller power consumption.

DESCRIPTION OF THE PRIOR ART

In a conventional 2-stage as shown on FIG. 1, input voltage is appliedto non-inverted input (IN), and the output (OUT) of the amplifyingcircuit is input to inverted input (INC) as negative feedback.Therefore, the circuit operates as a buffer, delivering input voltage(IN) as output signal (OUT) without change. Although not shown on FIG.1, the load (capacitive or resistive) driven by the amplifying circuitis connected to the output (OUT).

FIG. 2 shows the result of simulation for input signal (IN) and outputsignal (OUT) when a capacitance load of 100 pF is connected between theoutput (OUT) and the ground (VSS) of the 2-stage amplifying circuit,with source voltage (VDD) of 5V. FIG. 3A and FIG. 3B are magnified viewsof region A and region B of FIG. 2. When a square wave of varying levelsfrom 0.1 to 4.9 is applied as input signal (IN), it can be seen thatthere is a delay of about 10 μsec for the output signal (IN) to reachthe level of the input signal (IN). This delay time is called “settlingtime” for amplifying circuit, and is one of the important performancecharacteristics of an amplifying circuit, determined by the loadcapacitance, consumption current and phase of the amplifying circuit.

In general amplifying circuits, the load capacitance connected to theoutput is fixed, and the amplifying circuit is designed to have asettling time that is optimal for the fixed load condition.

For example, when a capacitive load of 10 nF is connected to the output(OUT) of the amplifying circuit in FIG. 1, the amplifying circuit willhave a settling time of more than 30 μsec, as shown on FIG. 4, FIG. 5Aand FIG. 5B. Therefore, in order to reduce the settling time to 10 μsecfor a amplifying circuit with 10 nF of capacitive load, it is necessaryto increase the size of the output transistors (P5, N5) shown on FIG. 1.

If the size of the output transistors (P5, N5) is more than quadrupledfor the purpose of reducing the settling time of the amplifying circuit,settling time is reduced to 20 μsec as shown on FIG. 6, FIG. 7A and FIG.7B, but the consumption current is increased by more than three times.

As described above, in a system where load capacitance is varyingbetween 100 pF and 10 nF, increasing the size of the output transistorof the amplifying circuit can reduce the settling time to a satisfactorylevel. However, this solution is difficult to use for a low powersystem, like mobile electronics, because the power consumption ofamplifying circuit is increased.

SUMMARY OF THE INVENTION

In order to solve the above-described problems, it is, therefore, anobject of the present invention to provide an amplifying circuit, whichenables variable load drivability responding to load conditions, anddrives variable load without increasing power consumption.

In accordance with an aspect of the present invention, there is providedan amplifying circuit that can change load drivability responding toload conditions, and reduce power consumption. The amplifying circuitaccording to the present invention comprises an amplifying means thatamplifies input signals a first time to generate a first and a secondamplified signals through a first and a second transistors, and furtheramplifies the first and second amplified signals once again through athird and a fourth transistors, for final outputs; a detecting means fordetecting the first and second amplified signals from the amplifyingmeans and generating a first and a second detection signals; and a loaddrivability control means that is controlled by the first and seconddetection signals from the detecting means to change load drivability ofthe amplifying means.

The amplifying circuit according to the present invention has theadvantage of reducing settling time by detecting changes when there arechanges in the input signal and increasing load drivability, andreducing power consumption by detecting no changes in the input signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and features of the instant invention willbecome apparent from the following description of preferred embodimentstaken in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic of conventional 2-stage amplifying circuit;

FIG. 2 is a waveform diagram of conventional 2-stage amplifying circuit;

FIG. 3A and FIG. 3B are magnified views of region A and region C of FIG.2;

FIG. 4 is a waveform diagram of the 2-stage amplifying circuit when loadcapacitor has a capacitance of 10 nF;

FIG. 5A and FIG. 5B are magnified views of region C and region D of FIG.4;

FIG. 6 is a waveform diagram of the 2-stage amplifying circuit when thesize of the output transistor is changed to four times the originalsize;

FIG. 7A and FIG. 7B are magnified views of region E and region F of FIG.6;

FIG. 8 is a schematic of a 2-stage amplifying circuit with variable loaddrivability according to the present invention;

FIG. 9 is a waveform diagram of the 2-stage amplifying circuit accordingto the present invention;

FIG. 10A and FIG. 10B are magnified view of region G and region H ofFIG. 9; and

FIG. 11 is a waveform diagram of the 2-stage amplifying circuit of FIG.8, according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, preferred embodiments of the present invention aredescribed in detail with reference to the drawings, so that thoseskilled in the art can easily understand the technical idea of thepresent invention.

FIG. 8 is a schematic of a 2-stage amplifying circuit according to anembodiment of the present invention.

In FIG. 8, the 2-stage amplifying circuit according to this embodimentis provided with an amplifying means (100) for outputting received inputsignals (IN) to the output stage (OUT) without change, a detecting means(200) for generating detection signals as it detects voltage levels inthe input signals (OUT1, OUT2) to the output transistors of PMOS type(P5) and NMOS type (N5) of the amplifying means (100), and a loaddrivability control means (300) for changing the load drivability of theamplifying means (100) in response to the detection signals from thedetection means (200).

The amplifying means (100) is a 2-stage amplifying circuit that firstamplifies input signals (IN), outputs them as stage-1 amplified signals(OUT1, OUT2) through the PMOS transistor (P4) and the NMOS transistor(N4), and amplifies them once again through another PMOS transistor (P5)and another NMOS transistor (N5), and outputs them through the outputstage (OUT). Its configuration and operation is the same as that of the2-stage amplifying circuit shown on FIG. 1.

The detecting means (200) comprises two Schmitt-trigger means (31, 32)that detect voltage level changes in the input signals (OUT1, OUT2) tothe output transistors of the amplifying means (100) (NMOS transistor(N5) and the PMOS transistor (P5)), and an exclusive OR gate (33) and aninverter (34) that receive the outputs from the Schmitt-trigger means(31, 32) and output detection signals (BSTX, BST) to control the loaddrivability control means (300).

The first and second Schmitt-trigger means (31, 32) output a low levelsignal (ground level) when the input signals (OUT1, OUT2) become thesame level as that of the gate signal (T2), i.e. the input signal to thePMOS transistor (P4) that outputs amplified signal (OUT2). The first andsecond Schmitt-trigger means (31, 32) output a high level signal (sourcevoltage level) when the input signals (OUT1, OUT2) become the same levelas that of the gate signal (T1), i.e. the input signal to the NMOStransistor (N4) that outputs amplified signal (OUT1).

The load drivability control means (300) comprises a first control means(310) that is driven by the detection signal (BST) of the detectionmeans (200) and increases the drivability of the output transistor (P5)of the amplifying circuit, and a second control means (320) that isdriven by the detection signal (BSTX) of the detection means (200) andincreases the drivability of the output transistor (N5) of theamplifying means (100).

The first control means (310) comprises an NMOS transistor (N6) and aPMOS transistor (P7) that function as switches, and a PMOS transistor(P8) that increases the load drivability in cooperation with the outputtransistor (P5) of the amplifying means (100) using the first amplifiedsignal (OUT1) as the gate input.

The second control means (320) comprises an NMOS transistor (N7) and aPMOS transistor (P6) that function as switches, and an NMOS transistor(N8) that changes the load drivability in cooperation with the outputtransistor (N5) of the amplifying means (100) using the second amplifiedsignal (OUT2) as the gate input.

The output transistors of the load drivability control means (300), i.e.PMOS transistor (P8) and the NMOS transistor (N8), have a size not lessthan four times that of output transistors of the amplifying means(100), i.e. the PMOS transistor (P5) and the NMOS transistor (N5).

The operation of the amplifying circuit with variable load drivabilityis described in the following, with reference to the input/outputwaveform diagram in FIG. 9, FIG. 10A and FIG. 10B, and the operationalwaveform diagram in FIG. 11.

First, when the input signal level (IN) to the amplifying circuit doesnot change, as in the settled region A, the amplified signal (OUT2)outputted from the PMOS transistor (P4) stays at the level of the gatesignal (T2) of the PMOS transistor (P4), and the amplified signal (OUT1)outputted from the NMOS transistor (N4) stays at the voltage level ofthe gate signal (T1). Therefore, the two Schmitt-trigger means (31, 32)respectively output high level signals of source voltage (VDD) level andlow level signals of ground level.

Therefore, the detecting means (200) generates a high level detectionsignal (BSTX) and a low level detection signal (BST) respectively,through an exclusive OR gate (33) and an inverter (34), and providesthem to the load drivability control means (300).

At the load drivability control means (300), the first control means(310) disables the PMOS transistor (P8) by turning on the PMOStransistor (P7) in response to the low level detection signal (BST), andthe second control means (320) disables the NMOS transistor (N8) byturning on the NMOS transistor (N7) in response to the high leveldetection signal (BSTX).

Also, because the amplified signals (OUT1, OUT2) are no longer deliveredto the gate inputs of the PMOS transistor (P8) and the NMOS transistor(N8) when the NMOS transistor (N6) and the PMOS transistor (P6) areturned off, the amplified signal from the PMOS transistor (P5) and theNMOS transistor (N5) of the amplifying means (100) are output throughthe output stage (OUT).

Next, when the input level of the amplifying circuit (IN) is greatlyincreased and fast operation of the output stage of the amplifyingcircuit is required, if the voltage at the output (OUT) is smaller thanthe voltage at-the input (IN), as in region B of FIG. 11, the amplifiedsignals (OUT1, OUT2) are lowered to the ground level (VSS).

Therefore, the Schmitt-trigger means (31) maintains the high levelsignal of source voltage (VDD) and the Schmitt-trigger means (32)generates the high level signal of source voltage (VDD). And theexclusive OR gate (33) and the inverter (34) respectively generates alow level detection signal (BSTX) and a high level detection signal(BST).

At the first control means (310) of the load drivability control means(300), the PMOS transistor (P6) is turned on by the low level detectionsignal (BSTX), and the amplified signal (OUT1) is delivered to the gateinput of the NMOS transistor (N8). At the second control means (320) ofthe load drivability control means (300), the NMOS transistor (N6) isturned on by the high level detection signal (BST), and the amplifiedsignal (OUT2) is delivered to the gate input of the PMOS transistor(P8).

Therefore, the size of the output stage transistors of the amplifyingcircuit becomes the sum of the sizes of all the PMOS transistors (P5,P8) and the NMOS transistors (N5, N8), which greatly increases the loaddrivability of the amplifying circuit, and greatly reduces the settlingtime compared with the conventional amplifying circuit, as shown on FIG.9, FIG. 10A and FIG. 1 b. The PMOS transistor (P7) and the NMOStransistor (N7) of the load drivability control means (300) are turnedoff by the detection signals (BST, BSTX).

When the load capacitor is charged, and the output (OUT) of theamplifying circuit approaches the level of the input signal (IN), andthe output signal (OUT) settles at the input signal level (IN), theamplified signal (OUT2) returns to the voltage level of the node (T2)from the ground level (VSS).

Therefore, when the level of the input signal (IN) does not change(region A) as described above, the output signal of the Schmitt-trigger(32) changes to a low level signal of ground level (VSS). This turns offthe PMOS transistor (P8) and the NMOS transistor (N8) of the loaddrivability control means (300) and reduces power consumption greatly.

Next, when the input signal level (IN) is lowered, like the region D inFIG. 11 where the output signal level (OUT) is greater than the inputsignal level (IN), the amplified signal (OUT1) approaches the sourcevoltage level (VDD), and the Schmitt-trigger means (31, 32) output highlevel signals of source voltage (VDD).

Accordingly, the exclusive OR gate (33) and the inverter (34)respectively output a low level detection signal (BSTX) and a high leveldetection signal (BST), and the PMOS transistor (P6) and the NMOStransistor (N6) of the load drivability control means (300) are turnedon.

Therefore, the size of the output stage transistor of the amplifyingcircuit becomes the sum of the sizes of all the PMOS transistors (P5,P8) and all the NMOS transistors (N5, N8), which greatly increases theload drivability of the amplifying circuit, and greatly reduces thesettling time compared with the conventional amplifying circuit, asshown on FIG. 9, FIG. 10A and FIG. 1 b.

When the load capacitor is discharged fast, the output signal level(OUT) of the amplifying circuit approaches the input signal-level (IN),and the output signal (OUT) settles at the level of input signal (IN) asin region E in FIG. 11, the amplified signal (OUT1) returns to the levelof node (T1) from the source voltage level (VDD).

Therefore, when the level of the input signal (IN) does not change (asin region E), the output signal of the Schmitt-trigger (31) changes to ahigh level signal of ground level (VDD). This turns off the PMOStransistor (P8) and the NMOS transistor (N8) of the load drivabilitycontrol means (300) and reduces the power consumption greatly.

In this embodiment of the present invention, the maximum current throughthe transistors (P5, N5, P8, N8) is decided by the W/L size of thesetransistors, which means that the settling time is decided by thesetransistors. Therefore, when the signal level of the amplified signal(OUT2) drops to the ground level (VSS), it is detected by the detectingmeans (200), which increases the drivability through the loaddrivability control means. When the amplifying circuit is almost settledand the amplified signal level (OUT2) returns to the signal level of thenode (T2), this is detected by the detecting means (200) and causes theload drivability control means (300) to be disabled.

When the amplified signal level (OUT1) rises to the source voltage level(VDD), it is detected by the detecting means (200), which increases thedrivability through the load drivability control means (300). When theamplifier circuit is almost settled and the amplified signal level(OUT1) returns to the source voltage level, this is detected by thedetecting means (200) and disables the load drivability control means(300). Therefore, when the input signal (IN) changes, the loaddrivability is increased to reduce the settling time, and when the inputsignal (IN) does not change, the power consumption is minimized.

As described above, according to the present invention, when there arechanges in input signal level (IN), it is detected, and causes the loaddrivability control means to increase the load drivability and to reducethe settling time, and when there is no change in the input signallevel, it is also detected and causes the load drivability control meansto be disabled, resulting in smaller power consumption.

Although the technical idea of the present invention has been describedin detail in connection with preferred embodiments, it should be obviousthat various modifications, additions and alterations may be made to theinvention by those skilled in the art without departing from the spiritand scope of the invention as defined in the appended claims.

1. An Amplifying circuit with variable load drivability, comprising: anamplifying means for amplifying input signals a first time through afirst and a second transistors to generate first and second amplifiedsignals and amplifying the first and second amplified signals a secondtime through a third and a fourth transistors to generate outputsignals; a detecting means for detecting the first and second amplifiedsignals from said amplifying means to generate a first and a seconddetection signals; and a load drivability control means controlled bythe first and second detection signals outputted from the detectingmeans for changing load drivability of the amplifying means, wherein thedetecting means further includes: a Schmitt-trigger means for detectingvoltage level change in the first and second amplified signals; anexclusive OR gate for receiving output signals from said Schmitt-triggermeans to generate the first detection signal; and an inverter forinverting the first detection signal to generate the second detectionsignal.
 2. The amplifying circuit with variable load drivability asrecited in claim 1, wherein said first arid second Schmitt-trigger meansoutput a low level signal at ground level if said first and secondamplified signals reach input signal level of said first transistor, andoutputs a high level signal of source voltage if said first and secondamplified signals reach input signal level of said second transistor. 3.The amplifying circuit with variable load drivability as recited inclaim 1, wherein said load drivability control includes: a first controlmeans that is driven by said second detection signal of said detectingmeans and increases drivability of said third transistor of saidamplifying means; and a second control means that is driven by saidfirst detection signal of said detecting means and increases drivabilityof said fourth transistor of said amplifying means.
 4. The amplifyingcircuit with variable load drivability as recited in claim 3, whereinthe first control means includes: a fifth transistor that increases loaddrivability in cooperation with said third transistor of said amplifyingmeans; a sixth transistor that disables said fifth transistor inresponse to said second detection signal; and a seventh transistor thatdelivers said first amplified signals to gate input of said fifthtransistor in response to said second detection signal.
 5. Theamplifying circuit with variable load drivability as recited in claim 4,wherein said fifth transistor of said first control means and said thirdtransistor of said amplifying means comprise PMOS transistors, and saidfifth transistor has a size not less than four (4) times that of saidthird transistor.
 6. The amplifying circuit with variable loaddrivability as recited in claim 4, wherein said sixth transistor andseventh transistors of said first control means comprise respectively aPMOS transistor and a NMOS transistor, both receiving said seconddetection signal as gate inputs.
 7. The amplifying circuit with variableload drivability as recited in claim 3, wherein said second controlmeans includes: an eighth transistor that increases load drivability incooperation with said fourth transistor of said amplifying means; aninth transistor that disables said eighth transistor in response tosaid second detection signals; and a tenth transistor that delivers saidsecond amplified signal to a gate input of said eighth transistor inresponse to said second detection signal.
 8. The amplifying circuit withvariable load drivability as recited in claim 7, wherein said eighthtransistor of said second control means and said fourth transistor ofsaid amplifying means comprise NMOS transistors, and said eighthtransistor has a size not less than four times that of said fourthtransistor.
 9. The amplifying circuit with variable load drivability asrecited in claim 7, wherein said ninth and tenth transistors of saidsecond control means respectively comprise a PMOS transistor and an NMOStransistor, both receiving said second detection signal as gate inputs.10. An Amplifying circuit with variable load drivability, comprising: anamplifying means for amplifying input signals a first time through afirst and a second transistors to generate first and second amplifiedsignals and the first and second amplified signals a second time througha third and a fourth transistors to generate output signals; a detectingmeans for detecting the first and second amplified signals from saidamplifying means to generate a first and a second detection signals; anda load drivability control means controlled by the first and seconddetection signals outputted from the detecting means for changing loaddrivability of the amplifying means, wherein said load drivabilitycontrol includes: a first control means that is driven by said seconddetection signal of said detecting means and increases drivability ofsaid third transistor of said amplifying means; and a second controlmeans that is driven by said first detection signal of said detectingmeans and increases drivability of said fourth transistor of saidamplifying means; wherein the first control means includes: a fifthtransistor that increases load drivability in cooperation with saidthird transistor of said amplifying means; a sixth transistor thatdisables said fifth transistor in response to said second detectionsignal; and a seventh transistor that delivers said first amplifiedsignals to gate input of said fifth transistor in response to saidsecond detection signal.
 11. The amplifying circuit with variable loaddrivability as recited in claim 10, wherein said fifth transistor ofsaid first control means and said third transistor of said amplifyingmeans comprise PMOS transistors, and said fifth transistor has a sizenot less than four (4) times that of said third transistor.
 12. Theamplifying circuit with variable load drivability as recited in claim10, wherein said sixth transistor and seventh transistors of said firstcontrol means comprise respectively a PMOS transistor and a NMOStransistor, both receiving said second detection signal as gate inputs.13. An Amplifying circuit with variable load drivability, comprising: anamplifying means for amplifying input signals a first time through afirst and a second transistors to generate first and second amplifiedsignals and the first and second amplified signals a second time througha third and a fourth transistors to generate output signals; a detectingmeans for detecting the first and second amplified signals from saidamplifying means to generate a first and a second detection signals; anda load drivability control means controlled by the first and seconddetection signals outputted from the detecting means for changing loaddrivability of the amplifying means, wherein said load drivabilitycontrol includes: a first control means that is driven by said seconddetection signal of said detecting means and increases drivability ofsaid third transistor of said amplifying means; and a second controlmeans that is driven by said first detection signal of said detectingmeans and increases drivability of said fourth transistor of saidamplifying means; wherein said second control means includes: an eighthtransistor that increases load drivability in cooperation with saidfourth transistor of said amplifying means; a ninth transistor thatdisables said eighth transistor in response to said second detectionsignals; and a tenth transistor that delivers said second amplifiedsignal to a gate input of said eighth transistor in response to saidsecond detection signal.
 14. The amplifying circuit with variable loaddrivability as recited in claim 13, wherein said eighth transistor ofsaid second control means and said fourth transistor of said amplifyingmeans comprise NMOS transistors, and said eighth transistor has a sizenot less than four times that of said fourth transistor.
 15. Theamplifying circuit with variable load drivability as recited in claim13, wherein said ninth and tenth transistors of said second controlmeans respectively comprise a PMOS transistor and an NMOS transistor,both receiving said second detection signal as gate inputs.